Elastic wave device, module

ABSTRACT

An elastic wave device includes a wiring board, a device chip having a resonator, and a wiring pattern electrically connected to the resonator, the device chip is electrically connected to the wiring board, and a sealing portion that seals the device chip. The wiring pattern includes a first wiring layer and a second wiring layer. The second wiring layer includes a lower metal layer in contact with an upper surface of the first wiring layer, a partition layer which is a metal layer in contact with an upper surface of the lower metal layer, and an upper metal layer in contact with an upper surface of the partition layer. The partition layer is a metal having a lower electrical conductivity than the lower metal layer and the upper metal layer.

CROSS REFERENCE TO RELATED APPLICATION(S)

This application claims priority to Japanese Patent Application No.2021-155157 filed Sep. 24, 2021, The aforementioned application isincorporated herein by reference, in its entirety, for any purpose.

BACKGROUND Field

The present disclosure relates to an elastic wave device and a modulecomprising the elastic wave device.

Background Art

Patent Document 1 (WO2011/089906) discloses an elastic wave device. Theelastic wave device can be provided as a high frequency filter having apassband frequency in the range of tens of MHz to several GHz. Theelastic wave device includes a piezoelectric substrate, a comb-shapedelectrode provided on an upper surface of the piezoelectric substrate, afirst wiring provided on the upper surface of the piezoelectricsubstrate, an organic insulator covering at least a portion of the firstwiring, a second wiring provided on a first portion of an upper surfaceof the organic insulator, and an inorganic insulator covering at least asecond portion of the upper surface of the organic insulator. Anexcitation space for exciting the piezoelectric substrate is formedabove the comb-shaped electrode, and the second portion of the uppersurface of the organic insulator faces the excitation space via theinorganic insulator.

The quality improvement of wiring structure is desired. For example, lowloss, high reliability, and high durability wiring structure isrequired.

SUMMARY

The present disclosure has been made to solve the above-describedproblems. An object of the present disclosure is to provide an elasticwave device having a wiring structure with enhanced quality, and amodule having the elastic wave device.

In some examples, an elastic wave device includes a wiring board, adevice chip having a resonator, and a wiring pattern electricallyconnected to the resonator, the device chip is electrically connected tothe wiring hoard, and a sealing portion that seals the device chip. Thewiring pattern includes a first wiring layer and a second wiring layer,the second wiring layer includes a lower metal layer in contact with anupper surface of the first wiring layer, a partition layer which is ametal layer in contact with an upper surface of the lower metal layer,and an upper metal layer in contact with an upper surface of thepartition layer. The partition layer is a metal having a lowerelectrical conductivity than the lower metal layer and the upper metallayer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a cross-sectional view of a wiring pattern;

FIG. 2 is a cross-sectional view showing a configuration example of anelastic wave device;

FIG. 3 is a plan view showing a configuration example of a device chip;

FIG. 4 is a plan view showing an example of elastic wave elements;

FIG. 5 is a sectional view showing an example of the wiring pattern;

FIG. 6A is a cross-sectional view of the wiring pattern of Examples;

FIG. 6B is a cross-sectional view of the wiring pattern structureaccording to Comparative Examples;

FIG. 7 is a table showing the wiring patterns of Examples andComparative Examples;

FIG. 8 is a graph showing simulation results of high-frequencyresistance values;

FIG. 9 shows measurement results of the attenuation amount of atransmission signal;

FIG. 10 shows a relationship between a frequency and the attenuation ofthe transmission signal;

FIG. 11 shows measurement results of the attenuation amount of areceived signal;

FIG. 12 is a diagram showing a relationship between a frequency and theattenuation of the received signal;

FIG. 13 is a diagram showing results of a bump shear strength test;

FIG. 14 is a cross-sectional view showing a configuration example of awiring pattern;

FIG. 15 shows a method for manufacturing the wiring pattern;

FIG. 16 shows a method for manufacturing the wiring pattern;

FIG. 17 shows a method for manufacturing the wiring pattern;

FIG. 18 shows a method for manufacturing the wiring pattern;

FIG. 19 shows a method for manufacturing the wiring pattern;

FIG. 20 shows a method for manufacturing the wiring pattern;

FIG. 21 is a cross-sectional view of an elastic wave device;

FIG. 22 shows an example of an acoustic thin film resonator; and

FIG. 23 is a cross-sectional view of a module having an elastic wavedevice.

DETAILED DESCRIPTION

Embodiments will be described with reference to the accompanyingdrawings. In the drawings, the same or corresponding parts are denotedby the same reference numerals. Duplicate descriptions of such portionsmay be simplified or omitted.

Embodiment 1

FIG. 1 is a cross-sectional view of a wiring pattern portion of anelastic wave device according to the Embodiment 1. According to oneexample, the representation of “a wiring pattern” or “a wiring layer”means an interconnect. On a piezoelectric substance 10, a wiring patternhaving a first wiring layer 12 and a second wiring layer 19 is formed.The first wiring layer 12 has a single metal layer or multiple metallayers. The second wiring layer 19 includes a lower metal layer 14 incontact with an upper surface of the first wiring layer 12, a partitionlayer 16 which is a metal layer in contact with an upper surface of thelower metal layer 14, and an upper metal layer 18 in contact with anupper surface of the partition layer 16. According to one example, thelower metal layer 14 comprises a single or multiple metal layers, andthe upper metal layer 18 also comprises a single or multiple metallayers. In the example of FIG. 1 , a width of the second wiring layer 19is smaller than a width of the first wiring layer 12. According to oneexample, the total thickness of the lower metal layer 14 and the uppermetal layer 18 may be 6 to 70 times the thickness of the first wiringlayer 12.

The partition layer 16 is a metal layer formed between the lower metallayer 14 and the upper metal layer 18. According to one example, thepartition layer 16 is a metal having a lower electrical conductivitythan the lower metal layer 14 and the upper metal layer 18. According toanother example, the partition layer 16 is a metal having a lowerelectrical conductivity than the first wiring layer 12, the lower metallayer 14 and the upper metal layer 18. For example, the partition layer16 is formed of any one or at least two selected from Ti, Mn, Pd, Cr,Pt, and Sn. Then, the lower metal layer 14 and the upper metal layer 18include any one or at least two selected from Ag, Cu, Au, Al, Be, and W.According to another example, the partition layer 16 is a metal havingan electrical conductivity of 10×10⁶ S/m or less, and the lower metallayer 14 and the upper metal layer 18 include a metal having anelectrical conductivity of 20×10⁶ S/m or more. According to one example,the partition layer 16 is in contact with a portion of the lower metallayer 14 having an electrical conductivity of 20×10⁶ S/m or more and aportion of the upper metal layer 18 having an electrical conductivity of20×10⁶ S/m or more. Also, the first wiring layer 12 may include a metalhaving an electrical conductivity of 20×10⁶ S/m or more.

According to one example, in order to electrically insulate the wiringpattern with adjacent conductors, an insulating layer 20 is formed. TheInsulating layer 20 is an insulator. In the example of FIG. 1 , theinsulating layer 20 is formed on the piezoelectric substance 10, a sidesurface of the first wiring layer 12, and a portion of the upper surfaceof the first wiring layer 12.

FIG. 2 is a cross-sectional view showing a configuration example of anelastic wave device. The elastic wave device 1 includes a wiring board2. According to an example, the wiring board 2 is a multilayer boardincluding a resin. According to another example, the wiring board 2 is aLow Temperature Co-fired Ceramics (LTCC) multilayer substrate made of aplurality of dielectric layers. A passive element such as a capacitor oran inductor may be formed inside the wiring board 2.

In the example of FIG. 2 , the wiring board 2 is provided with aplurality of conductive pads 2 b, The plurality of conductive pads 2 bare provided on an upper surface of the wiring board 2. Accordingly, theupper surface of the wiring board 2 serves as a component mountingsurface. A lower surface of the wiring board 2 is, for example, amounting surface to a mother substrate. A plurality of conductive pads 2c are provided on a lower surface of the wiring board 2. The conductivepads 2 b and the conductive pads 2 c corresponding to each other areconnected by an inner conductor 2 a or via hole conductor.

Above the wiring board 2, there is a device chip 3 which is electricallyconnected to the wiring board 2, The device chip 3 is, for example, asurface acoustic wave device chip. The device chip 3 is provided with apiezoelectric substrate 3 a formed of a piezoelectric material. Thepiezoelectric substrate 10 described above is a part of thepiezoelectric substrate 3 a. According to an example, the piezoelectricsubstrate 3 a is a substrate formed of a piezoelectric single crystalsuch as lithium tantalate, lithium niobate or quartz. According toanother example, the piezoelectric substrate 3 a is a substrate for tiedof piezoelectric ceramics. According to yet another example, thepiezoelectric substrate 3 a is a substrate to which the piezoelectricsubstrate and a support substrate are bonded. The support substrate is,for example, a substrate formed of sapphire, silicon, alumina, spinel,quartz, or glass.

According to an example, the piezoelectric substrate 3 a is a substrateon which the functional element is formed. For example, a receivingfilter and a transmission filter are formed on a main surface (a lowersurface) of the device chip 3. The main surface faces the wiring board2.

The receiving filter is formed so that an electrical signal in a desiredfrequency band can pass. For example, the receiving filter is aladder-type filter consisting of a plurality of series resonators and aplurality of parallel resonators.

The transmission filter is formed so that an electrical signal in adesired frequency band can pass. For example, the transmission filter isa ladder-type filter consisting of a plurality of series resonators anda plurality of parallel resonators.

In the example of FIG. 2 , a wiring pattern 3 b and a plurality ofelectrodes 3 c formed periodically are formed on the main surface of thedevice chip 3. According to an example, the plurality of electrodes 3 care Interdigital Transducer (IDT) electrodes, which are comb-shapedelectrode fingers. Surface acoustic waves are excited by applying a highfrequency electric field to the IDT electrodes through a wiring patternfrom the lead terminal on the power supply side. Filter characteristicscan be obtained by converting the surface acoustic waves into highfrequency electric fields by piezoelectric action.

The wiring pattern 3 b and the conductive pad 2 b are electricallyconnected by a hump 4. The hump 4 is, for example, Au, a conductiveadhesive or solder.

The elastic wave device 1 includes a sealing portion 5. According to oneexample, the sealing portion 5 is a resin that seals the device chip 3while leaving a space 6 between the wiring hoard 2 and the device chip3. According to an example, the device chip 3 is mounted on the wiringhoard 2. Subsequently, a resin sheet is placed on the device chip 3. Forexample, the resin sheet is prepared by forming liquid epoxy resin intoa sheet. According to another example, the resin sheet may be asynthetic resin such as poly imide different from an epoxy resin. Aprotective film made of polyethylene terephthalate (PET) can be providedon an upper surface of the resin sheet. A base film made of polyestercan be provided on a lower surface of the resin sheet. By placing theresin sheet on the device chip 3, the resin sheet is temporarily fixedto the device chip 3. Thereafter, the resin sheet is heated to asoftening temperature to fill the side surface of the device chip 3 andthe upper surface of the wiring board 2 with the resin sheet. This iscalled the heated roller lamination method. Thereafter, the resin sheetis heated to a curing temperature of the resin to completely cure.

According to one example, the device chip 3 has a plurality ofresonators. The plurality of resonators can be a surface acoustic waveresonator. In this case, the device chip 3 can function as a band-passfilter or a duplexer.

FIG. 3 is a plan view showing a configuration example of the device chip3 and the wiring board 2. As shown in FIG. 3 , a plurality of elasticwave elements 30 and a plurality of wiring patterns 32 are formed on themain surface of the device chip 3. The plurality of elastic waveelements 30 includes a plurality of series resonators S1, S2, S3, S4, S5and a plurality of parallel resonators P1, P2, P3, P4.

According to one example, the plurality of series resonators S1, S2, S3,S4, S5 and the plurality of parallel resonators P1, P2, P3, P4 areformed so as to function as a transmission filter, A receiving filterhaving other series resonators and other parallel resonators may beformed in the device chip 3.

In one example, the wiring patterns 32 are formed of a suitable metal oralloy such as silver, aluminum, copper, titanium, palladium, or thelike. According to one example, at least a portion of the wiringpatterns 32 has the wiring pattern structure of FIG. 1 . According toanother example, all the wiring patterns 32 has the wiring patternstructure of FIG. 1 . The thickness of the wiring patterns 32 is, forexample, 1500 nm to 4500 nm.

The wiring patterns 32 are electrically connected to respective elasticwave elements 30. The wiring patterns 32 include an antenna bump padANT, a transmission bump pad Tx, a receiving bump pad Rx and four groundbump pads GND. These bump pads are portions that are electricallyconnected to the bumps when they are mounted. The wiring patterns 32includes not only these hump pads, but also wiring portions connectingthe bump pads and the elastic wave elements 30.

FIG. 4 is a diagram showing an example of one of the elastic waveelements 30, As shown in FIG. 4 , an IDT31 and a pair of reflectors 39are formed on a main surface of the device chip 3. The IDT 31 and thepair of reflectors 39 are provided so as to excite surface-acousticwaves.

According to one example, the IDT31 and the pair of reflectors 39 areformed of aluminium-copper alloys. According to another example, theIDT31 and the pair of reflectors 39 are formed of titanium, palladium,silver or alloys thereof. According to still another example, the IDT31and the pair of reflectors 39 are formed by a laminated metal film inwhich a plurality of metal layers are laminated. The IDT31 and the pairof reflectors 39 may be formed of different materials. For example, Timay be added to the upper and lower surfaces of the materials describedabove. According to one example, the thickness of the IDT31 and the pairof reflectors 39 is between 150 nm and 400 nm.

The IDT 31 includes a pair of comb-shaped electrodes 31 a. The pair ofcomb-shaped electrodes 31 a are opposed to each other. Each of thecomb-shaped electrodes 31 a includes a plurality of electrode fingers 31h and a bus bar 31 c. The plurality of electrode fingers 31 b arearranged in its longitudinal direction. The bus bar 31 c connects theplurality of electrode fingers 31 b. When viewed in plan, the IDT31 issandwiched between the pair of reflectors 39. According to one example,the IDT31 and the pair of reflectors 39 can be the same material as thefirst wiring layer 12 of FIG. 1 . In that case, the IDT31, the pair ofreflectors 39 and the first wiring layer 12 are deposited and patternedin the same process.

According to one example, such a SAW (Surface Acoustic Wave) resonatoris electrically connected to the wiring pattern. Further, the devicechip is electrically connected to the wiring board. The input signalfrom the wiring board is filtered by the device chip and outputs to thewiring board.

FIG. 5 is a sectional view showing an example of the wiring pattern. Thefirst wiring layer 12 has a structure in which a Ti layer 12 a, an AlCulayer 12 b and a Ti layer 12 c are stacked in the order presented. Thelower metal layer 14 has a structure in which a Ti layer 14 a and an Allayer 14 h are stacked in the order presented. In this example, thepartition layer 16 is made of Ti. The upper metal layer 18 is made ofAl.

According to an example, the wiring pattern may be formed on a substratehaving a piezoelectric substrate 10 a and a substrate 10 b. Thesubstrate 10 b is in contact with the lower surface of the piezoelectricsubstrate 10 a. According to one example, a resonator and the wiringpattern are formed on the upper surface of the piezoelectric substrate10 a. The substrate 10 b is made of, for example, sapphire, silicon,alumina, spinel, quartz, or glass. In the example of FIG. 5 , the devicechip comprises the piezoelectric substrate 10 a and the substrate 10 b.

Examples and Comparative Examples will be described with reference toFIGS. 6A-13 . FIG. 6A is a cross-sectional view of the wiring pattern ofExamples. FIG. 6B is a cross-sectional view of the wiring patternstructure according to Comparative Examples. FIG. 6A shows the wiringpattern having the first wiring layer 12, a Ti layer, an Al layer, a Tilayer, and an Al layer. Specifically, the Ti layer, the Al layer, the Tilayer, and the Al layer are formed in this order on the first wiringlayer 12. FIG. 6B shows the wiring pattern structure having the firstwiring layer 12, a Ti layer, and an Al layer. The Ti layer and the Allayer are formed in this order on the first wiring layer 12. In bothExamples (FIG. 6A) and Comparative Examples (FIG. 6B), the first wiringlayer 12 has a Ti layer, a AlCu layer, and a Ti layer on top of thepiezoelectric substrate. In other words, in both Examples (FIG. 6A) andComparative Examples (FIG. 6B), the first wiring layer 12 has the samelayer structure as the IDT.

FIG. 7 is a table showing the layer thicknesses of the respective layersof Examples and Comparative Examples. In Comparative Example 1, athickness of the outermost Al layer is 1500 nm, whereas in ComparativeExample 2, a thickness of the outermost Al layer is 4000 nm. Thepartition layers 16 of Examples 1-4 are different in thickness. Athickness of the partition layer 16 is 110 nm in Example 1, 115 nm inExample 2, 120 nm in Example 3, and 150 nm in Example 4.

FIG. 8 is a graph showing simulation results of high-frequencyresistance values of Example 1 and Comparative Example 2. FIG. 8 showsthat the high-frequency resistance value of Example 1 is lower than thehigh-frequency resistance value of the Comparative Example 2 at anyfrequency from 0.5 GHz to 8 GHz. Therefore, the wiring structure ofExample 1 has less wiring loss than that of Comparative Example 2 and issuitable as a wiring of a high-frequency device.

FIG. 9 shows measurement results of the attenuation amount of atransmission signal for Comparative Examples and Examples. Twenty-onesamples were prepared for each of the wiring structures of ComparativeExamples 1 and 2 and Examples 1 to 4. The attenuation of thetransmission signal was measured for these samples and is shown in FIG.9 . From FIG. 9 , it can be seen that the signal loss can be suppressedmore in Comparative Example 2 than in Comparative Example 1. Therefore,the signal loss can be suppressed by thickening the Al layer of thelower metal layer 14. Further, it is understood that the wiringstructure of Examples 1 to 4 has less signal loss than that ofComparative Examples 1 and 2. Therefore, thickening the second wiringlayer by providing the partition layer 16 and the upper metal layer 18can suppress attenuation of the transmission signal compared to simplythickening the Al layer of the lower metal layer 14 as in ComparativeExample 2. Comparing Examples 1-4, there was a tendency that Example 1had the smallest signal loss, Example 2 had a larger signal loss thanExample 1, Example 3 had a larger signal loss than Example 2, andExample 4 had a larger signal loss than Example 3, Therefore, as awiring pattern for reducing the loss of the transmission signal, it isconsidered to be effective to reduce the thickness of the partitionlayer 16.

FIG. 10 is a diagram showing a relationship between a frequency and theattenuation of the transmission signal. FIG. 10 shows the frequencydependence of the attenuation of the transmission signal for ComparativeExample 1 and Example 1. It can be seen from FIG. 10 that the wiringstructure of Example 1 has less attenuation of the transmission signalat any frequency compared to the wiring structure of Comparative Example1.

FIG. 11 shows measurement results of the attenuation amount of areceived signal for Comparative Examples and Examples. Twenty-onesamples were prepared for each of the wiring structures of ComparativeExamples 1 and 2 and Examples 1 to 4. The attenuation of the receivedsignal was measured for these samples and is shown in FIG. 11 . FromFIG. 11 , it can be seen that the signal loss can be suppressed more inExamples 1-4 than in Comparative Examples 1, 2. Further, it isunderstood that the wiring structure of Comparative Example 2 has lesssignal loss than that of Comparative Example 1. Therefore, the signalloss can be suppressed by thickening; the Al layer of the lower metallayer 14. However, thickening the second wiring layer by providing thepartition layer 16 and the upper metal layer 18 can suppress attenuationof the received signal compared to simply thickening the Al layer of thelower metal layer 14 as in Comparative Example 2.

FIG. 12 is a diagram showing a relationship between a frequency and theattenuation of the received signal. FIG. 12 shows the frequencydependence of the attenuation of the received signal for ComparativeExample 1 and Example 1. It can be seen from FIG. 12 that the wiringstructure of Example 1 has less attenuation of the received signal atany frequency compared to the wiring structure of Comparative Example 1.

FIG. 13 is a diagram showing results of a bump shear strength test ofthe bumps. First, a bump is formed on the wiring pattern. The bump shearstrength test was then performed to test the bonding properties of thebumps. The sample that gave the leftmost result in FIG. 13 is a baseline(BL: reference) sample (hereinafter referred to as a BL sample). The BLsample is a sample in which an Al layer having a thickness of 1.5 μm isused as a wiring pattern and humps are funned thereon. From FIG. 13 , itcan be seen that in the BL sample, since the wiring pattern is thin, theshear strength is relatively good.

In the case of Comparative Example 2, the lower metal layer 14 includesan Al layer having a thickness of 4.0 μm. In this case, the bump shearstrength deteriorated as compared with other samples. ComparativeExample 3 is a wiring pattern similar to the wiring pattern of Example 1of FIG. 7 . But Comparative Example 3 is different from the wiringstructure of Example 1 of FIG. 7 in that a part of the partition layer16 contacting the lower metal layer 14 (i.e. Ti layer of 10 nm) isomitted. Therefore, the wiring patterns of Comparative Example 3 andExamples 1 to 4 differ in the thickness of the Ti layer of the partitionlayer 16. When the thicknesses of the partition layers 16 are arrangedin ascending order, Comparative Example 3. Example 1, Example 2, Example3. Example 4 are obtained. It can be seen from FIG. 13 that the wiringpatterns of Comparative Example 3 and Examples 1 to 4 all givesufficient bump share strength. Assuming that the requirement value forbump share strength is 14.2 gf, all samples listed in FIG. 13 meet thisrequirement value. However, in Comparative Example 2, there was a cleardecrease tendency in the hump share strength as compared withComparative Example 3 and Examples 1-4. The wiring pattern ofComparative Example 2 is thickened only by an Al layer. In ComparativeExample 2, the decreased bump shear strength is considered to be causedby a thick Al—Au compound. The thick Al—Au compound may be generatedfrom the Al layer and the Au bump, and voids and grain coarsening occur.On the other hand, in Comparative Example 3 and Examples 1 to 4, apartition layer 16 was added between the two Al layers to thicken thewiring pattern. In this case, the formation of the compound of the Allayer and the Au hump is suppressed by the partition layer. Therefore, agood bump shear strength can be obtained. Thus, by adding the partitionlayer as the intermediate layer of the wiring pattern, a high bump shearstrength can be obtained.

Embodiment 2

FIG. 14 is a cross-sectional view showing a configuration example of awiring pattern according to the Embodiment 2. A first insulating layer40 covers a portion of the upper surface of the first wiring layer 12.The lower metal layer 14 has a portion in contact with the upper surfaceof the first wiring layer 12, and a portion in contact with the uppersurface of the first wiring layer 12 via the first insulating layer 40.A second insulating layer 42 covers an upper surface of the firstinsulating layer 40 and the side surface of the second wiring layer 19.According to one example, the second insulating layer 42 exposes atleast a portion of the upper surface of the upper metal layer 18.

The second wiring layer 19 of FIG. 14 is formed in a stepped shape. Thesecond insulating layer 42 covers the stepped shape. In the example ofFIG. 14 , the first wiring layer 12 is not in direct contact with thesecond insulating layer 42. The second wiring layer 19 is in directcontact with the first wiring layer 12, the first insulating layer 40and the second insulating layer 42. The first insulating layer 40 is indirect contact with the first wiring layer 12, the second wiring layer19 and the second insulating layer 42. Thus, the wiring pattern of FIG.14 is covered by the first insulating layer 40 and the second insulatinglayer 42. According to an example, a thermal expansion coefficient ofthe first insulating layer 40 can be made smaller than a thermalexpansion coefficient of the second insulating layer 42. As a result ofthis, peeling of the second insulating layer 42 can be suppressed.

A width X1 shown in FIG. 14 is the difference in width of the firstwiring layer 12 and the lower metal layer 14. The width X1 is, forexample, 1.5 μm. A width X2 is the overlapping width of the firstinsulating layer 40 and the lower metal layer 14. The width X2 is, forexample, 2.0 μm. A width X3 is the overlapping width of the secondinsulating layer 42 and the partition layer 16. The width X3 is, forexample, 2.0 μm. A width X4 is the overlapping width of the secondinsulating layer 42 and the upper metal layer 18, The width X4 is, forexample, 2.0 μm.

A method of manufacturing the wiring pattern according to the Embodiment2 will be described with reference to FIGS. 15-20 . First, the firstwiring layer 12 is patterned to form the first insulating layer 40.Next, as shown in FIG. 15 , a first photo-resist PR1 is formed. Thefirst photoresist PR1 exposes a portion of the first insulating layer 40and a portion of the first wiring layer 12.

Next, the lower metal layer 14 is formed. FIG. 16 is a cross-sectionalview showing that the lower metal layer 14 is formed. According to oneexample, the lower metal layer 14 includes a Ti layer and a AlCu layerformed over the Ti layer. For example, the thickness of the Ti layer is100 nm, and the thickness of the AlCu layer is 1500 nm. With theformation of the lower metal layer 14, a metal layer 14 a is also formedon the first photo-resist PR1.

Next, a first lift-off process is performed. As a result, the firstphoto-resist PR1 and the metal layer 14 a are removed. FIG. 17 is across-sectional view after the first lift-off process. Next, a secondphoto-resist is formed. FIG. 18 is a diagram showing the secondphoto-resist PR2. The second photo-resist PR2 exposes a portion of thelower metal layer 14.

Next, the partition layer 16 and the upper metal layer 18 are formed.FIG. 19 is a view showing that the partition layer 16 and the uppermetal layer 18 are formed. According to one example, the partition layer16 is a Ti layer having a thickness of 100 nm, and the upper metal layer18 is a AlCu layer having a thickness of 1500 nm. With the for formationof the partition layer 16 and the upper metal layer 18, a metal layer 17is formed on the second photo-resist PR2.

Next, a second lift-off process is performed. As a result, the secondphoto-resist PR2 and the metal layers 17 are removed. FIG. 20 is across-sectional view after the second lift-off process. Next, the secondinsulating layer 42 is formed as necessary. According to thismanufacturing method, a width of the partition layer 16 matches a widthof the upper metal layer 18. According to another example, as shown inFIG. 14 , a width of the partition layer 16 and a width of the lowermetal layer 14 may coincide with each other.

Embodiment 3

FIG. 21 is a longitudinal cross-sectional view of an elastic wave deviceaccording to the Embodiment 3. As shown in FIG. 21 , an elastic wavedevice 50 comprises a first device chip 51 and a second device chip 52.According to an example, the first device chip 51 and the second devicechip 52 function as a band-pass filter. For example, the first devicechip 51 functions as one of a transmission filter and a receivingfilter. The second device chip 52 functions as the other of thetransmission filter and the receiving filter.

The first device chip 51 and the second device chip 52 can havesubstantially the same configuration as the device chip 3 of theEmbodiment 1. The first device chip 51 includes, for example, theplurality of elastic wave elements 30 of the Embodiment 1. Specifically,the first device chip 51 can include a band-pass filter made of aplurality of surface acoustic wave resonators. The second device chip 52includes, for example, the plurality of elastic wave elements 30 of theEmbodiment 1. Specifically, the second device chip 52 can includes aband-pass filter made of a plurality of surface acoustic waveresonators.

According to another example, the second device chip 52 includes elasticwave elements different from that of Embodiment 1. Specifically, thesecond device chip 52 may have a band-pass filter made of a plurality ofacoustic thin film resonators.

FIG. 22 shows an example in which the elastic wave element of the seconddevice chip 52 is an acoustic thin film resonator. In FIG. 22 , thesecond device chip 52 includes a chip substrate 60. The chip substrate60 is, for example, a semiconductor substrate such as silicon, or aninsulating substrate such as sapphire, alumina, spinel or glass. Apiezoelectric film 62 is provided on the chip substrate 60. Thepiezoelectric film 62 is formed of, for example, aluminum nitride. Alower electrode 64 and an upper electrode 66 are provided so as tosandwich the piezoelectric film 62. The lower electrode 64 and the upperelectrode 66 are formed of a metal such as ruthenium, for example. Anair gap 68 is a space between the lower electrode 64 and the chipsubstrate 60. In the acoustic thin film resonator, the lower electrode64 and the upper electrode 66 excite an elastic wave having a thicknesslongitudinal vibration mode inside the piezoelectric film 62. In thiscase, the second device chip 52 has a plurality of resonators, and theresonators function as an acoustic thin film resonator. The seconddevice chip 52 may function as a bandpass filter or a duplexer.

According to the Embodiment 3 described above, a band-pass filter madeof a plurality of surface acoustic wave resonators can be formed in thesecond device chip 52. Further, a band-pass filter made of a pluralityof acoustic thin film resonators can be formed in the second device chip52. The aforementioned wiring pattern may be employed in both the firstdevice chip 51 and the second device chip 52.

Embodiment 4

FIG. 23 is a longitudinal cross-sectional view of a module 100 having anelastic wave device. The module 100 includes a wiring board 130, anintegrated circuit component IC, an elastic wave device 101, an inductor111, and a sealing portion 117. According to an example, the wiringboard 130 can be equivalent to the wiring board 2 described in theEmbodiment 1. The integrated circuit component IC is mounted inside thewiring board 130. According to one example, the integrated circuitcomponent IC includes a switching circuit and a low noise amplifier.

The elastic wave device 101 is mounted on the main surface of the wiringboard 130. As the elastic wave device 101, any of the several elasticwave devices described above can be employed. That is, the wiringpattern of the elastic wave device 101 includes the partition layer 16.

The inductor 111 is mounted on the main surface of the wiring board 130.The inductor 111 is mounted for impedance matching. For example, theinductor 111 may be an Integrated Passive Device (IPD). The sealingportion 117 seals a plurality of electronic components including theelastic wave device 101.

While several aspects of at least one embodiment have been described, itis to be understood that various modifications and improvements willreadily occur to those skilled in the art. Such modifications andimprovements are intended to be part of the present disclosure and areintended to be within the scope of the present disclosure.

It is to be understood that the embodiments of the methods and apparatusdescribed herein are not limited in application to the structural andordering details of the components set forth in the foregoingdescription or illustrated in the accompanying drawings. Methods andapparatus may be implemented in other embodiments or implemented invarious manners.

Specific implementations are given here for illustrative purposes onlyand are not intended to be limiting.

The phraseology and terminology used in the present disclosure are forthe purpose of description and should not be regarded as limiting. Theuse of “including,” “comprising,” “having,” and variations thereofherein means the inclusion of the items listed hereinafter andequivalents thereof, as well as additional items.

The reference to “or” may be construed so that any term described using“or” may be indicative of one, more than one, and all of the terms ofthat description.

References to front, back, left, right, top, bottom, and side areintended for convenience of description. Such references are notintended to limit the components of the present disclosure to any onepositional or spatial orientation. Accordingly, the foregoingdescription and drawings are by way of example only.

1. An elastic wave device, comprising: a wiring board; a device chiphaving a resonator, and a wiring pattern electrically connected to theresonator, the device chip is electrically connected to the wiringhoard; and a sealing portion that seals the device chip, wherein thewiring pattern includes a first wiring layer and a second wiring layer,the second wiring layer includes a lower metal layer in contact with anupper surface of the first wiring layer, a partition layer which is ametal layer in contact with an upper surface of the lower metal layer,and an upper metal layer in contact with an upper surface of thepartition layer, and the partition layer is a metal having a lowerelectrical conductivity than the lower metal layer and the upper metallayer.
 2. The elastic wave device according to claim 1, wherein a totalthickness of the lower metal layer and the upper metal layer is 6 to 70times a thickness of the first wiring layer.
 3. The elastic wave deviceaccording to claim 1, further comprising a first insulating layer thatcovers a portion of the upper surface of the first wiring layer, whereinthe lower metal layer has a portion in contact with the upper surface ofthe first wiring layer, and a portion in contact with the upper surfaceof the first wiring layer via the first insulating layer.
 4. The elasticwave device according to claim 3, further comprising a second insulatinglayer that covers an upper surface of the first insulating layer and aside surface of the second wiring layer.
 5. The elastic wave deviceaccording to claim 4, wherein the second wiring layer has a steppedshape, and the second insulating layer covers the stepped shape.
 6. Theelastic wave device according to claim 4, wherein the first wiring layeris not in direct contact with the second insulating layer.
 7. Theelastic wave device according to claim 4, wherein the second wiringlayer is in direct contact with the first wiring layer, the firstinsulating layer and the second insulating layer.
 8. The elastic wavedevice according to claim 4, wherein the first insulating layer is indirect contact with the first wiring layer, the second wiring layer andthe second insulating layer.
 9. The elastic wave device according toclaim 4, wherein a thermal expansion coefficient of the first insulatinglayer is smaller than a thermal expansion coefficient of the secondinsulating layer.
 10. The elastic wave device according to claim 1,wherein a width of the second wiring layer is smaller than a width ofthe first wiring layer.
 11. The elastic wave device according to claim1, wherein the device chip comprises a piezoelectric substrate and asubstrate connected to a lower surface of the piezoelectric substrate,wherein the resonator and the wiring pattern are formed on an uppersurface of the piezoelectric substrate, and wherein the substrate isformed of sapphire, silicon, alumina, spinel, quartz, or glass.
 12. Theelastic wave device according to claim 1, wherein the device chip has aplurality of resonators, the plurality of resonators is a surfaceacoustic wave resonator, and the device chip functions as a band-passfilter or a duplexer.
 13. The elastic wave device according to claim 1,wherein the device chip has a plurality of resonators, the plurality ofresonators is a plurality of acoustic thin film resonators, and thedevice chip functions as a band-pass filter or a duplexer.
 14. Theelastic wave device according to claim 1, wherein the first wiring layerhas a structure in which a Ti layer, an AlCu layer and a Ti layer arestacked in the order presented, the lower metal layer has a structure inwhich a Ti layer and an Al layer are stacked in the order presented, thepartition layer is made of Ti, and the upper metal layer is made of Al.15. The elastic wave device according to claim 1, wherein the partitionlayer is a metal having an electrical conductivity of 10×10⁶ S/m orless, and the lower metal layer and the upper metal layer include ametal having an electrical conductivity of 20×10⁶ S/m or more.
 16. Amodule comprising the elastic wave device according to claim 1.